1. Field of the invention
The present invention relates to a logic circuit, and more specifically to a scan path circuit for testing a sequential circuit driven with a multi-phase clock.
2. Description of related art
In general, since it is more difficult to test a sequential circuit internally provided in a logic circuit, than to test a combinational circuit, various logic circuit designs have been attempted. Of these attempted logic circuit designs, a scan path circuit for making it possible to observe flipflops provided in the sequential circuit by supplying values to these flipflops from an external, is particularly widely used. However, a conventional scan path circuit is disadvantageous in that the circuit malfunctions because of a clock skew at the time of shifting, or the circuit cannot operate as a multi-phase clock driven sequential circuit at a non-testing time.
Japanese Patent Laid-open Publication No. Heisei 3-180198, the disclosure of which is incorporated by reference in its entirety into the present application, discloses a logic integrated circuit having a scan circuit designed to overcome the problem caused by the clock skew at the time of shifting, and to be able to operate with a multi-phase clock. This logic integrated circuit is so configured that first and second clocks and a first test clock signal are supplied to two selectors which are controlled by a test mode signal, so that at a non-testing time, each flipflop is driven by a corresponding one of the first and second clock signals, and at a testing time, each flipflop is driven by the first test clock signal and a second test clock signal.
However, this conventional logic circuit cannot test the first and second clock signals since these first and second clock signals are not used at the testing time. In addition, this conventional logic circuit has a restriction in design that each flipflop must be driven by a positive going clock. In many cases, the logic integrated circuits are generally designed to be driven with a multi-phase clock, and therefore, the test circuit for the sequential circuit is required to comply with such logic integrated circuits. In addition, this constituents included in the circuit must be able to be tested. However, the above mentioned conventional logic circuit cannot test the normal clock signals if the test clock signals am selected by the test mode signal.